Event-driven spiking neural networks with in-memory computing — neuromorphic chips and systems that far outpace GPU efficiency on matching tasks.
Not another
GPU. It's a brain.
BPU (Brain Processing Unit) refers to spike/event-driven neuromorphic computing chips and systems. Its core goal is to provide native hardware support for SNN neuron updates, synaptic event propagation, and event routing/scheduling — constructing scalable brain-inspired computing systems through asynchronous AER (Address-Event Representation) communication.
TrueNorth, Loihi, and more recent wafer-scale neuromorphic systems are all representatives of this class. On tasks matching its paradigm — event streams, sparse temporal signals, online learning — BPU far outpaces traditional GPU efficiency.
Compute only on actual spikes
Skip invalid dense MAC sweeps
Moving data costs more than computing
If "computing efficiency" means effective task volume per unit power, BPU typically significantly outperforms GPU on tasks matching its paradigm.
Efficiency depends on whether the task can be expressed as a sparse event-driven SNN and efficiently mapped to BPU neuron/synapse models.
From PCIe accelerator card to wafer-scale server — choose the right BPU form factor for your task scale.
Single or few BPU chips packaged as cards / development platforms, connected via PCIe to host. Easy integration into existing server workflows with low barriers.
BPU chiplet modular packaging, flexibly integrable into various computing platforms for higher-density brain-inspired compute.
Wafer-scale neuromorphic system with on-wafer short-distance high-density interconnects. Significant advantages in large-scale event communication and energy efficiency.
Prototyping, small-scale apps. Easy workflow integration.
Mid-scale apps. Flexible integration, customizable.
Ultra-large brain simulation. Billion-neuron scale, near-biological efficiency.
A breakthrough wafer-scale neuromorphic computing system — interconnected on a single wafer into a unified event-driven compute network.
Wafer-scale BPU computing interconnects numerous brain-inspired chips (or chiplets) on a single wafer into a unified event-driven system. Computation remains fundamentally SNN neuron state updates and synaptic event propagation — but scaled to "wafer-level neuron-synapse totals." Events transmit at high speed via asynchronous AER, with hierarchical timesteps or GALS synchronization ensuring temporal consistency across chiplets.
On-wafer short-distance high-density interconnects replace PCB-level long connections, significantly reducing bandwidth, latency and power penalties.
Brings large-scale SNN and brain simulations closer to biological system efficiency in power-latency metrics.
Events transmitted at high speed via asynchronous AER, with GALS synchronization ensuring temporal consistency.
Supports near-brain-scale parallel spiking computation with billion-neuron parallel processing.
BPU is best suited for scenarios where inputs are naturally event streams or sparsifiable, and decisions depend heavily on temporal structure.
Large-scale neuroscience circuit simulation with billion-neuron parallel processing.
Event-based visual perception processing with ultra-low latency real-time response.
Ultra-low latency real-time control and online learning for IoT and embedded scenarios.
Radar / sonar / tactile sensor integration with unified multi-modal event stream processing.
Common thread: strong requirements for low latency, low power, sparse temporal processing, or online plasticity.
Self-developed LYRArc-II memory-computing fusion processing architecture, supports BI-Link brain-inspired computing card interconnect expansion, supports full-range neuron connections, supports variable computing precision (FP32/FP16/INT8), featuring high flexibility, high processing efficiency, high interconnect bandwidth, and ultra-low communication latency.
Self-developed LYRArc-II memory-computing fusion processing architecture, self-developed integrated assembly technology for computing, power supply, cooling, and interconnect, supports BI-Link system-level expansion interconnect, supports variable computing precision (FP32/FP16/INT8).
Supports over 400 million neuron simulation computing
Self-developed ultra-high computing density integrated technology (4U with 16 LBM212 BPU acceleration cards), self-developed brain-inspired vascular phase-change liquid cooling technology, supports BI-Link brain-inspired computing card interconnect, supports variable computing precision (FP32/FP16/INT8), operating noise below 65dB.
4U space integrates 16 LBM212 cards, ultra-high computing density
